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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9831270 B1

PDFFull Text
Date of Patent:
Nov. 28, 2017

Filed:

Mar. 16, 2017

Nonvolatile semiconductor memory device and method for manufacturing the same

Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Gaku Sudo, Mie, JP;

Yumiko Miyano, Tokyo, JP;

Assignee:

Toshiba Memory Corporation, Tokyo, JP;

Attorney:

Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Primary Examiner:

Walter H Swanson

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

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