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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9831244 B1

PDFFull Text
Date of Patent:
Nov. 28, 2017

Filed:

Aug. 28, 2015

Method for manufacturing a semiconductor device

Applicants:

Ju-youn Kim, Suwon-si, KR;

Je-don Kim, Seoul, KR;

Inventors:

Ju-Youn Kim, Suwon-si, KR;

Je-Don Kim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Julia Slutsker

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28088 (2013.01); H01L 21/28247 (2013.01); H01L 21/76801 (2013.01); H01L 21/76829 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 29/0642 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/45 (2013.01); H01L 29/4966 (2013.01); H01L 29/511 (2013.01); H01L 29/66545 (2013.01); H01L 21/02068 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/76897 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

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