The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Jun. 07, 2017
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Shintaro Izumi, Kobe, JP;

Tomoki Nakagawa, Kobe, JP;

Hiroshi Kawaguchi, Kobe, JP;

Masahiko Yoshimoto, Kobe, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 29/08 (2006.01); G11C 11/22 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0072 (2013.01); G11C 11/221 (2013.01); G11C 11/2259 (2013.01); G11C 29/08 (2013.01); G11C 29/50 (2013.01);
Abstract

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.


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