The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Oct. 17, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chang-kyo Lee, Seoul, KR;

Won-young Lee, Seongnam-si, KR;

Bo-bae Shin, Suwon-si, KR;

Jung-hwan Choi, Hwaseong-si, KR;

Yong-cheol Bae, Yongin-si, KR;

Seok-hun Hyun, Seongnam-si, KR;

Min-su Ahn, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtung-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01);
Abstract

A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.


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