The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Jan. 14, 2014
Applicant:

Nec Corporation, Tokyo, JP;

Inventors:

Masashi Ogawa, Tokyo, JP;

Manabu Kusumoto, Tokyo, JP;

Hisashi Ishida, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5036 (2013.01); G06F 2217/78 (2013.01);
Abstract

A design support device having a permissible power supply fluctuation deriving unit and a target impedance deriving unit. The permissible power supply fluctuation deriving unit derives the fluctuation in the power supply voltage that is permissible on the basis of jitter-voltage correlation information, which indicates the correlation between the power supply voltage fluctuation generated in an I/O buffer and the jitter generated by the power supply voltage fluctuations, and jitter constraint information, which is for stably transmitting a signal, for the generated jitter. The target impedance deriving unit derives a target impedance in the permissible range of impedance for a power supply circuit, on the basis of information on the signal operating current flowing through the power supply circuit of the I/O buffer, and the power supply voltage fluctuation.


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