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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9830242 B1

PDFFull Text
Date of Patent:
Nov. 28, 2017

Filed:

Oct. 13, 2015

Loading calculation method and loading calculation system for processor in electronic device

Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Ran-How Chen, Hsinchu County, TW;

Ming-Fang Tsai, Hsinchu County, TW;

Chih-Jen Tsai, Taoyuan, TW;

Hsin-Hsien Huang, Hsinchu County, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Charles Swift

Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 17/00 (2006.01); G06N 5/00 (2006.01); G06N 5/02 (2006.01); G06F 11/30 (2006.01); G06F 11/00 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 11/30 (2013.01); G06F 9/48 (2013.01); G06F 9/4843 (2013.01); G06F 11/00 (2013.01); G06F 11/3003 (2013.01); G06F 11/3006 (2013.01); G06F 11/3024 (2013.01); G06N 5/00 (2013.01); G06N 5/02 (2013.01); G06N 5/022 (2013.01);
Abstract

The present invention provides a loading calculation method and a loading calculation system for a processor in an electronic device is disclosed. The loading calculation system comprises: a detecting unit, a determining unit, a generating unit, and a calculating unit. The loading calculation method comprises: detecting a plurality of switching actions of the processor to generate a detecting result; determining a time interval to separate the detecting result to generate a plurality of time periods; generating a log file of scheduling according to the detecting result and the plurality of time periods; utilizing the processor for enabling the log file of scheduling; and calculating the processor loading according to the log file of scheduling.

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Chen, Ran-How. (2017). Loading calculation method and loading calculation system for processor in electronic device (U.S. Patent No. 9830242). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9830242

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