The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Jun. 05, 2015
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Russell A. Blaine, San Carlos, CA (US);

Daniel A. Chimene, San Francisco, CA (US);

Shantonu Sen, Cupertino, CA (US);

John Dorsey, San Francisco, CA (US);

Bryan Hinch, Mountain View, CA (US);

Cyril De La Cropte De Chanterac, San Francisco, CA (US);

Olivier Cozelle, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4843 (2013.01); G06F 9/4881 (2013.01); G06F 9/4893 (2013.01); G06F 9/5027 (2013.01); G06F 9/5094 (2013.01); G06F 9/52 (2013.01);
Abstract

In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general 'importance' of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.


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