Performing on-chip partial good die identification

Abstract

In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.