The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Apr. 05, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jae Hwan Seo, Gyeonggi-do, KR;

Woo Yeol Shin, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 1/073 (2006.01); H01L 21/66 (2006.01); H01L 23/498 (2006.01); G01R 1/04 (2006.01);
U.S. Cl.
CPC ...
G01R 1/07378 (2013.01); H01L 22/00 (2013.01); H01L 23/49827 (2013.01); G01R 1/0483 (2013.01); H01L 23/49811 (2013.01);
Abstract

An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.


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