The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Jun. 06, 2016
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventor:

Jeffery Beck, Philomath, OR (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H04N 5/357 (2011.01); H04N 5/355 (2011.01); H04N 5/359 (2011.01); H04N 5/365 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3575 (2013.01); H04N 5/3577 (2013.01); H04N 5/3592 (2013.01); H04N 5/35518 (2013.01); H04N 5/365 (2013.01); H04N 5/378 (2013.01);
Abstract

An imaging pixel may be operated in either a linear mode or a logarithmic mode. In the logarithmic mode, the voltage at a floating diffusion region may be proportional to the logarithm of the intensity of incident light. In order to enable correlated double sampling (CDS) in the logarithmic mode, a transistor may be provided that couples the photodiode to a bias voltage. When the transistor is turned off, the photodiode may be able to operate in a logarithmic mode. When the transistor is turned on, the floating diffusion region may be reset to a baseline voltage level. Images from the linear mode and the logarithmic mode may be combined to form high dynamic range images with flicker mitigation.


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