The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
Nov. 30, 2016
Applicant:
Futurewei Technologies, Inc., Plano, TX (US);
Inventors:
Iulin Lih, San Jose, CA (US);
William Lynch, Los Altos, CA (US);
Assignee:
Futurewei Technologies, Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/24 (2006.01); H04L 12/721 (2013.01); H04L 12/437 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01); H04L 12/42 (2006.01); H04L 12/715 (2013.01); H04L 12/741 (2013.01);
U.S. Cl.
CPC ...
H04L 45/12 (2013.01); G06F 15/17362 (2013.01); G06F 15/7825 (2013.01); H04L 12/42 (2013.01); H04L 12/437 (2013.01); H04L 45/06 (2013.01); H04L 45/64 (2013.01); H04L 45/745 (2013.01); H04L 2012/421 (2013.01); Y02B 60/1207 (2013.01); Y02B 60/1225 (2013.01);
Abstract
An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring.