The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Mar. 31, 2016
Applicant:

Lsis Co., Ltd., Gyeonggi-do, KR;

Inventors:

Seung-Cheol Choi, Gyeonggi-do, KR;

An-No Yoo, Gyeonggi-do, KR;

Assignee:

LSIS CO., LTD., Gyeonggi-Do, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/483 (2007.01); H02M 7/487 (2007.01); H02M 5/458 (2006.01); H02M 1/32 (2007.01); H02M 7/49 (2007.01);
U.S. Cl.
CPC ...
H02M 5/458 (2013.01); H02M 1/32 (2013.01); H02M 7/487 (2013.01); H02M 7/49 (2013.01); H02M 2001/325 (2013.01);
Abstract

The present disclosure relates to a multi-level inverter capable of performing a bypass operation without adding any separate module. The multi-level inverter includes a first capacitor and a second capacitor coupled in series to each other, a plurality switches for generating a multi-level output voltage by using a voltage charged in the first capacitor and the second capacitor and a plurality of diodes respectively coupled in parallel to the plurality of switches, a first output terminal and a second output terminal for outputting the output voltage, and a controller for switching a state of each of the plurality of switches to an on or off state according to one of predetermined bypass modes, thereby interrupting the output of the output voltage through the first output terminal and the second output terminal.


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