The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
Dec. 30, 2014
Glf Integrated Power, Inc., Santa Clara, CA (US);
Stephen W. Bryson, Cupertino, CA (US);
Ni Sun, Sunnyvale, CA (US);
GLF Integrated Power, Inc., Santa Clara, CA (US);
Abstract
A fully integrated circuit configuration that can be used to control the power path of a number of PMOS load switches is described. The circuit has a unique feature that it can automatically select the input voltage to be presented to the VOUT pin based upon the voltage levels at the respective VIN pins. By using combinations of the EN input pin and the SEL input pin, the circuit can be configured to perform one of four functional behaviors: 1. Complete shutdown (both switches in the OFF position), 2. Automatic input selection according the voltage levels that are presented on the VIN pins, 3. Selection of the VIN1 input only, or 4. Selection of the VIN2 input only. This concept is extended to multiple input sources in further embodiments.