The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Mar. 15, 2016
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Cheng Hua Lin, Hsinchu, TW;

Yan-Liang Ji, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/0619 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/0886 (2013.01); H01L 29/66681 (2013.01); H01L 29/42368 (2013.01); H01L 29/665 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.


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