The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Sep. 16, 2015
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tomohiro Tamaki, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/868 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 29/0634 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01); H01L 29/66727 (2013.01); H01L 29/7396 (2013.01); H01L 29/868 (2013.01); H01L 29/8611 (2013.01); H01L 29/0615 (2013.01); H01L 29/0638 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/41766 (2013.01); H01L 29/872 (2013.01);
Abstract

Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.


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