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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9824946 B1

PDFFull Text
Date of Patent:
Nov. 21, 2017

Filed:

Aug. 09, 2016

Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-Yong Byun, Seoul, KR;

Ho-Sung Song, Seoul, KR;

Chi-Wook Kim, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Caridad Everhart

Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 31/2884 (2013.01); G01R 31/2894 (2013.01); H01L 21/78 (2013.01); H01L 22/14 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01);
Abstract

A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

Find Patent Forward Citations

Byun, Young-Yong. (2017). Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level (U.S. Patent No. 9824946). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9824946

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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