Feedback validation of arbitrary non-volatile memory data

Abstract

An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell. The process continues until all addresses in the memory array have been evaluated, following which the reference level identifies the strength of the weakest cell in the array, and the weakest address can be identified.