The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

May. 08, 2012
Applicants:

Christopher Edward Koob, Round Rock, TX (US);

Ajay Anant Ingle, Austin, TX (US);

Lucian Codrescu, Austin, TX (US);

Suresh K. Venkumahanti, Austin, TX (US);

Inventors:

Christopher Edward Koob, Round Rock, TX (US);

Ajay Anant Ingle, Austin, TX (US);

Lucian Codrescu, Austin, TX (US);

Suresh K. Venkumahanti, Austin, TX (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0842 (2016.01); G06F 12/0846 (2016.01); G06F 12/0864 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0842 (2013.01); G06F 12/0848 (2013.01); G06F 12/0864 (2013.01);
Abstract

Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.


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