The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
Apr. 27, 2017
Applicant:
Cavium, Inc., San Jose, CA (US);
Inventors:
Muhammad Raghib Hussain, Saratoga, CA (US);
Rajan Goyal, Saratoga, CA (US);
Richard Kessler, Northborough, MA (US);
Assignee:
Cavium, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 3/06 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/0637 (2013.01); G06F 3/0644 (2013.01); G06F 3/0664 (2013.01); G06F 9/455 (2013.01); G06F 9/5077 (2013.01);
Abstract
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.