The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Apr. 27, 2016
Applicant:
Yale University, New Haven, CT (US);
Inventors:
Xiao Sun, New Haven, CT (US);
Tso-Ping Ma, Branford, CT (US);
Assignee:
Yale University, New Haven, CT (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/11 (2006.01); H01L 29/66 (2006.01); G11C 11/22 (2006.01); H01L 27/1159 (2017.01); H01L 27/11597 (2017.01);
U.S. Cl.
CPC ...
H01L 29/6684 (2013.01); G11C 11/223 (2013.01); H01L 27/1159 (2013.01); H01L 27/11597 (2013.01); H01L 29/78391 (2014.09);
Abstract
Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.