The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Dec. 07, 2015
Applicants:

Ki-seok OH, Seoul, KR;

Doo-hee Hwang, Seongnam-si, KR;

Dong-yang Lee, Yongin-si, KR;

Jong-hyun Choi, Suwon-si, KR;

Inventors:

Ki-Seok Oh, Seoul, KR;

Doo-Hee Hwang, Seongnam-si, KR;

Dong-Yang Lee, Yongin-si, KR;

Jong-Hyun Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 27/18 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); H01L 25/0657 (2013.01); H01L 27/18 (2013.01); H01L 27/222 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/10 (2013.01); G11C 2207/105 (2013.01); H01L 2224/09515 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.


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