The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Mar. 09, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Young-Ja Kim, Cheonan-si, KR;
Bongchan Kim, Seongnam-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 9/00 (2006.01); H05K 13/00 (2006.01); H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 24/97 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/3025 (2013.01);
Abstract
Provided is a method of fabricating a semiconductor package. The method includes providing a substrate including a plurality of semiconductor chips; forming a mold layer covering the semiconductor chips; forming a first shielding layer on the mold layer; cutting the mold layer and the first shielding layer to form trenches between the semiconductor chips; and forming a second shielding layer to fill the trenches.