The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Jul. 06, 2016
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Chun-Li Liu, Scottsdale, AZ (US);

Ali Salih, Mesa, AZ (US);

Balaji Padmanabhan, Tempe, AZ (US);

Mingjiao Liu, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 23/373 (2006.01); H01L 33/62 (2010.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/3735 (2013.01); H01L 23/49524 (2013.01); H01L 23/49531 (2013.01); H01L 23/49555 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 24/73 (2013.01); H01L 25/072 (2013.01); H01L 33/62 (2013.01); H01L 29/2003 (2013.01); H01L 2224/40 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/73265 (2013.01);
Abstract

In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.


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