The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Aug. 31, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Amilcar R. Arvelo, Poughkeepsie, NY (US);

Michael J. Ellsworth, Lagrangeville, NY (US);

Eric J. McKeever, Poughkeepsie, NY (US);

Thong N. Nguyen, Poughkeepsie, NY (US);

Edward J. Seminaro, Milton, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/40 (2006.01); H01L 23/367 (2006.01); H05K 3/30 (2006.01); H01L 23/42 (2006.01); H01L 23/34 (2006.01); H01L 23/473 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/34 (2013.01); H01L 23/42 (2013.01); H01L 23/473 (2013.01); H05K 3/30 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely encase the module except for a connector passing through the bottom plate. The cold plate has copper tubing pressed into a groove formed in a serpentine pattern. The perimeter of the cold plate has thermal conduction fins which mate with thermal conduction slots in the perimeter of the bottom plate. Thermal interface material is disposed in gaps between the plates and chips on the module, the gaps having dimensions controlled by support ribs of plates which abut the module substrate. The cold plate is used on the hottest side of the module, e.g., the side having computationally-intensive chips such as ASICs. A densely packed array of these packages can be used in a central electronic complex drawer with a shared coolant circulation system.


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