The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Jun. 25, 2014
Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Taku Horii, Osaka, JP;

Takeyoshi Masuda, Osaka, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02694 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 21/02664 (2013.01); H01L 21/046 (2013.01); H01L 21/047 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7811 (2013.01);
Abstract

A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.


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