The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Jun. 22, 2015
Applicant:

The Hong Kong University of Science and Technology, Hong Kong, CN;

Inventors:

Hoi Sing Kwok, New Territories, HK;

Man Wong, New Territories, HK;

Rongsheng Chen, Kowloon, HK;

Meng Zhang, Kowloon, HK;

Wei Zhou, Kowloon, HK;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 21/02 (2006.01); H01L 29/786 (2006.01); H01L 29/16 (2006.01); H01L 29/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02672 (2013.01); H01L 21/02532 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/32 (2013.01); H01L 29/786 (2013.01); H01L 21/02422 (2013.01); H01L 21/02592 (2013.01);
Abstract

Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.


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