The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Jan. 27, 2011
Masae Kitayama, Osaka, JP;
Mitsuaki Hirata, Osaka, JP;
Fumikazu Shimoshikiryoh, Osaka, JP;
Kenichi Hyodo, Osaka, JP;
Ikumi Itsumi, Osaka, JP;
Yuki Yamashita, Osaka, JP;
Akane Sugisaka, Osaka, JP;
Masae Kitayama, Osaka, JP;
Mitsuaki Hirata, Osaka, JP;
Fumikazu Shimoshikiryoh, Osaka, JP;
Kenichi Hyodo, Osaka, JP;
Ikumi Itsumi, Osaka, JP;
Yuki Yamashita, Osaka, JP;
Akane Sugisaka, Osaka, JP;
SHARP KABUSHIKI KAISHA, Sakai, JP;
Abstract
A color display pixel Pin a liquid crystal display device () includes first through fourth pixels Pthrough Parrayed in two rows by two columns, and first and second signal lines () which are located in correspondence with each column of pixels and are supplied with signal voltages of polarities opposite to each other from a signal line driving circuit () in each vertical scanning period. A TFT () of one of the first and third pixel Pand Pis connected to the first signal line (), and a TFT () of the other pixel is connected to the second signal line (). A TFT () of one of the second and fourth pixel Pand Pis connected to the first signal line (), and a TFT () of the other pixel is connected to the second signal line (). The TFTs () of the first through fourth pixels Pthrough Pare controlled to be ON/OFF by a common scanning signal, and the polarities of the signal voltages supplied to the first and second signal lines () are constant during an arbitrary vertical scanning period. Owing to this, the load on the signal line driving circuit is reduced.