The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9817696 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 14, 2017

Filed:

Feb. 24, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bruce Mealey, Austin, TX (US);

Suresh E. Warrier, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/45558 (2013.01); G06F 9/5038 (2013.01); G06F 9/5044 (2013.01); G06F 2009/4557 (2013.01);
Abstract

A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.


Find Patent Forward Citations

Mealey, Bruce. (2017). Low latency scheduling on simultaneous multi-threading cores (U.S. Patent No. 9817696). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9817696

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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