The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Dec. 08, 2015
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Aws Shallal, Santa Clara, CA (US);

Dan Kunkel, Santa Clara, CA (US);

Assignee:

INPHI CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0685 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01);
Abstract

An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.


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