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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9817434 B1

PDFFull Text
Date of Patent:
Nov. 14, 2017

Filed:

Jan. 06, 2016

Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Bo-Geun Kim, Suwon-si, KR;

Kye-Hyun Kyung, Yongin-si, KR;

Jae-Yong Jeong, Yongin-si, KR;

Seung-Hun Choi, Yongin-si, KR;

Seok-Cheon Kwon, Yongin-si, KR;

Chul-Ho Lee, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:

Volentine & Whitt, PLLC

Primary Examiner:

Thomas Lee

Assistant Examiner:

Zhipeng Wang

Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 13/42 (2006.01); H04L 5/00 (2006.01); H04L 7/00 (2006.01); G06F 1/14 (2006.01); G06F 1/32 (2006.01); G06F 13/16 (2006.01); G06F 1/04 (2006.01); G11C 7/22 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/04 (2013.01); G06F 1/14 (2013.01); G06F 1/3203 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0683 (2013.01); G06F 13/1689 (2013.01); G11C 7/222 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

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