The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Jan. 23, 2017
Applicant:

Celerint, Llc, New York, NY (US);

Inventor:

Howard H. Roberts, Jr., Austin, TX (US);

Assignee:

CELERINT, LLC., New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/28 (2006.01); G01R 31/26 (2014.01); G01R 1/04 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2834 (2013.01); G01R 1/0433 (2013.01); G01R 31/2601 (2013.01); G01R 31/2893 (2013.01);
Abstract

A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.


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