The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Oct. 14, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Timothy Patrick Pauletti, Plano, TX (US);

Sameer Pendharkar, Dallas, TX (US);

Wayne Tien-Feng Chen, Plano, TX (US);

Jonathan Brodsky, Richardson, TX (US);

Robert Steinhoff, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 27/02 (2006.01); H01L 29/74 (2006.01); H01L 29/87 (2006.01); H01L 29/749 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 29/7436 (2013.01); H01L 29/87 (2013.01); H01L 29/749 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.


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