The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Apr. 20, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jung Pill Kim, San Diego, CA (US);

Dexter Tamio Chun, San Diego, CA (US);

Jungwon Suh, San Diego, CA (US);

Deepti Vijayalakshmi Sriramagiri, San Diego, CA (US);

Yanru Li, San Diego, CA (US);

Mosaddiq Saifuddin, San Diego, CA (US);

Xiangyu Dong, San Jose, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 29/44 (2006.01); G11C 29/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 11/401 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/073 (2013.01); G06F 11/079 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); G06F 11/1048 (2013.01); G11C 29/42 (2013.01); G11C 29/76 (2013.01); G11C 11/401 (2013.01);
Abstract

A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.


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