The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Dec. 28, 2016
Applicant:

Aucmos Technologies Usa, Inc., Santa Clara, CA (US);

Inventors:

Tianhong Yan, Saratoga, CA (US);

Yung-Tin Chen, Santa Clara, CA (US);

Assignee:

AUCMOS Technologies USA, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); H01L 27/11 (2006.01); H01L 27/11502 (2017.01);
U.S. Cl.
CPC ...
G11C 14/0072 (2013.01); H01L 27/1104 (2013.01); H01L 27/11502 (2013.01);
Abstract

A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.


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