The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

May. 06, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Nobuyasu Kanekawa, Tokyo, JP;

Hitoshi Arimitsu, Kanagawa, JP;

Takashi Yasumasu, Kanagawa, JP;

Hideki Matsuyama, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 11/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2053 (2013.01); G06F 11/165 (2013.01); G06F 11/1616 (2013.01); G06F 11/1641 (2013.01); G06F 11/183 (2013.01); G06F 11/187 (2013.01); G06F 2201/85 (2013.01);
Abstract

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.


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