The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Jul. 12, 2016
Applicant:

Linear Technology Corporation, Milpitas, CA (US);

Inventors:

Richard William Ezell, Lucas, TX (US);

Eric Wright Mumper, Plano, TX (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); H03L 7/23 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/10 (2013.01); H03L 7/23 (2013.01);
Abstract

A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.


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