The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Aug. 19, 2016
Applicant:

Faraday Technology Corporation, Hsinchu, TW;

Inventors:

Yuan-Min Hu, Hsinchu, TW;

Jhen-Yu Hou, Hsinchu, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03D 3/24 (2006.01); H04L 27/00 (2006.01); H03K 3/00 (2006.01); H03L 7/00 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H04L 27/0014 (2013.01); H03K 3/00 (2013.01); H03L 7/00 (2013.01); H03L 7/08 (2013.01); H04L 2027/0036 (2013.01);
Abstract

A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.


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