The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Apr. 20, 2016
Applicant:

Rf Micro Devices, Inc., Greensboro, NC (US);

Inventors:

Philip W. Mason, Greensboro, NC (US);

Michael Carroll, Jamestown, NC (US);

Julio C. Costa, Oak Ridge, NC (US);

Jan Edward Vandemeer, Kernersville, NC (US);

Daniel Charles Kerr, Oak Ridge, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 23/66 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01);
Abstract

The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.


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