The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Nov. 30, 2015
Applicant:
Veeco Instruments, Inc., Plainview, NY (US);
Inventors:
Jie Su, Metuchen, NJ (US);
George Papasouliotis, Warren, NJ (US);
Assignee:
Veeco Instruments, Inc., Plainview, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 21/0254 (2013.01); H01L 21/02639 (2013.01); H01L 21/02647 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01);
Abstract
Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.