The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Feb. 23, 2015
Applicants:

Anup Bhalla, Santa Clara, CA (US);

Daniel Ng., Campbell, CA (US);

Tiesheng LI, San Jose, CA (US);

Sik K. Lui, Sunnyvale, CA (US);

Inventors:

Anup Bhalla, Santa Clara, CA (US);

Daniel Ng., Campbell, CA (US);

Tiesheng Li, San Jose, CA (US);

Sik K. Lui, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66712 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/66719 (2013.01); H01L 29/66727 (2013.01); H01L 29/7802 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01);
Abstract

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.


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