The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Jul. 17, 2015
Applicant:
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Inventors:
Kinya Ohtani, Kanagawa, JP;
Kenji Okada, Kanagawa, JP;
Yasuhiro Nishimura, Kanagawa, JP;
Noriaki Mukaide, Kanagawa, JP;
Assignee:
Renesas Electronics Corporation, Kawasaki-shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42372 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/7813 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/7802 (2013.01); H01L 29/7816 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.