The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jan. 30, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Takuya Inatsuka, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11526 (2017.01); H01L 27/11548 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 21/78 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first layers and second layers that are alternately formed. The substrate has a memory region extending in first and second directions along a surface of the substrate, a step region adjacent to the memory region in the first direction, and a peripheral region adjacent to the memory region and the step region in the second direction. The insulating layers and the wiring layers are formed on the memory region and the step region. The first and second layers are formed on the peripheral region. Each of the first layers is formed on a same level as and in contact with one of the insulating layers, and each of the second layers is formed on a same level as and in contact with one of the wiring layers.


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