The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jun. 05, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Han-Sik Yoo, Seoul, KR;

Hyuk-Joon Kwon, Yongin-si, KR;

Jung-Ha Oh, Gwacheon-si, KR;

Jun-Ho Kim, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); G11C 11/56 (2006.01); G11C 29/52 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); G11C 16/04 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 29/04 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); G06F 11/1048 (2013.01); G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 29/52 (2013.01); H01L 23/528 (2013.01); H01L 27/10814 (2013.01); H01L 28/40 (2013.01); G11C 29/42 (2013.01); G11C 2029/0411 (2013.01); H01L 27/11582 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.


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