The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jan. 20, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jae-yeol Song, Seoul, KR;

Wan-don Kim, Yongin-si, KR;

Oh-seong Kwon, Hwaseong-si, KR;

Hyeok-jun Son, Seoul, KR;

Sang-jin Hyun, Hwaseong-si, KR;

Hoon-joo Na, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/82345 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 29/0653 (2013.01);
Abstract

Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.


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