The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Sep. 09, 2012
Jean Fompeyrine, Rueschlikon, CH;
Edward W. Kiewra, Verbank, NY (US);
Steven J. Koester, Ossining, NY (US);
Devendra K. Sadana, Pleasentville, NY (US);
David J. Webb, Rueschlikon, CH;
Jean Fompeyrine, Rueschlikon, CH;
Edward W. Kiewra, Verbank, NY (US);
Steven J. Koester, Ossining, NY (US);
Devendra K. Sadana, Pleasentville, NY (US);
David J. Webb, Rueschlikon, CH;
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AONprior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.