The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Feb. 28, 2017
Osaka University, Suita-shi, Osaka, JP;
Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;
Heiji Watanabe, Osaka, JP;
Takayoshi Shimura, Osaka, JP;
Takuji Hosoi, Osaka, JP;
Mitsuru Sometani, Tsukuba, JP;
OSAKA UNIVERSITY, Suita-Shi, Osaka, JP;
FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;
Abstract
A p-type base region, n-type source region, p-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.