The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Feb. 06, 2013
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Hiroki Funato, Tokyo, JP;

Takashi Suga, Tokyo, JP;

Yoshiyuki Tsuchie, Tokyo, JP;

Satoshi Nakamura, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5009 (2013.01); G06F 17/5036 (2013.01); G01R 29/0814 (2013.01); Y02T 10/82 (2013.01);
Abstract

An object of the present invention is to provide an EMC design technique of a device including an electronic device mounted therein for implementing noise amount analysis of a system in which individual electronic devices are combined. A housing model is acquired, component models are selected and acquire, the acquired component models are connected using a wire, the acquired component models are arranged in the acquired housing model, the arranged component models connected using the wire is driven to generate electromagnetic noise from the component models and the wire, the generated electromagnetic noise is propagated in the housing model to calculate a noise amount, and an output process of outputting data of the calculated noise amount is performed. Thus, even in the system in which a plurality of electronic devices are combined, electromagnetic noise analysis of the system can be easily performed, and a noise reduction design can be supported.


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