The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Mar. 19, 2014
Proplus Electronics Co., Ltd., Jinan, CN;
Bruce W. McGaughy, Pleasanton, CA (US);
Zhaozhi Yang, Beijing, CN;
PROPLUS DESIGN SOLUTIONS, INC., San Jose, CA (US);
Abstract
Methods and systems are disclosed related to dynamic load balancing in circuit simulation. In one embodiment, a computer implemented method of performing dynamic load balancing in simulating a circuit includes identifying a plurality of simulation tasks to be performed, determining estimated processing durations corresponding to performance of the plurality of simulation tasks, distributing the plurality of simulation tasks to a plurality of processors according to the estimated processing duration of each simulation task, and performing the plurality of simulation tasks at the plurality of processors in parallel.