The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Mar. 14, 2011
Applicants:

Richard Roy Grisenthwaite, Nr Royston, GB;

David James Seal, Cherry Hinton, GB;

Philippe Jean-pierre Raphalen, Valbonne, FR;

Lee Douglas Smith, Cambridge, GB;

Inventors:

Richard Roy Grisenthwaite, Nr Royston, GB;

David James Seal, Cherry Hinton, GB;

Philippe Jean-Pierre Raphalen, Valbonne, FR;

Lee Douglas Smith, Cambridge, GB;

Assignee:

ARM LIMITED, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 9/40 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 21/57 (2013.01); G06F 21/70 (2013.01);
U.S. Cl.
CPC ...
G06F 9/3016 (2013.01); G06F 9/3001 (2013.01); G06F 9/30112 (2013.01); G06F 9/3861 (2013.01); G06F 21/577 (2013.01); G06F 21/70 (2013.01); G06F 2221/2145 (2013.01);
Abstract

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.


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