The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Mar. 12, 2015
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Masato Hayashi, Tokyo, JP;

Chihiro Yoshimura, Tokyo, JP;

Masanao Yamaoka, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 99/00 (2010.01); G06F 7/58 (2006.01); G06N 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 7/588 (2013.01); G06N 7/005 (2013.01); G06N 99/00 (2013.01); G06N 99/002 (2013.01);
Abstract

A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested. An information processing system includes: a host unit equipped with one or more semiconductor chips that execute a ground-state search of an Ising model; and an operation unit that provides a user interface for a user to designate a problem; and a management unit that converts the problem designated by the user by using the user interface into the Ising model and controls the host unit to have the semiconductor chip perform the ground-state search of the converted Ising model; wherein the user can designate a condition for solving the problem by using the user interface; wherein the management unit generates an operating condition of the semiconductor chip according to the condition designated by the user and reports the generated operating condition and the Ising model of the problem designated by the user to the host unit; and wherein the host unit controls the semiconductor chip in accordance with the operating condition reported from the management unit.


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